Method for fabricating semiconductor device

ABSTRACT

A method for forming a p-channel metal-oxide semiconductor(PMOS) device is suitable for reducing the width of change of a threshold voltage by preventing a deterioration of a uniformity of dopants due to out diffusion and segregation of the dopants implanted into channel regions. The method includes the steps of: forming a channel region below a surface of a semiconductor substrate; activating dopants implanted into the channel region through a first annealing process performed twice by rising temperature velocities different to each other; forming a gate oxidation layer and a gate electrode on the semiconductor substrate subsequently; forming a source/drain regions at both sides of the gate electrode in the semiconductor substrate; and activating dopants implanted into the source/drain regions through a second annealing process performed at the same conditions of the first annealing process.

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor memory device;and, more particularly, to a method for fabricating a semiconductordevice having an improved channel characteristics.

DESCRIPTION OF RELATED ART

[0002] As the semiconductor device has been integrated, a channel lengthbecomes to decrease. Although the size of the device becomes to reduce,concentrations of source and drain are still very high to improve avelocity thereof.

[0003] A short channel length allows a threshold voltage(VT) to fallrapidly as a distance between a source and a drain becomes short. Thefalling of the threshold voltage(VT) increases a leakage current at anatmosphere and generates a punch of the source and the drain todeteriorate the device characteristics. Specifically, in a p-channelmetal-oxide semiconductor(PMOS) device major carriers are holes, amobility of carriers of the PMOS is low 3 times in comparison with thatof carrier, i.e., electrons, of an n-channel metal-oxidesemiconductor(NMOS). Therefore, controls of concentration and positionsof channel dopants and segregation from a field oxidation layer in thechannel become very important.

[0004]FIG. 1A is a cross-sectional diagram showing a PMOS device inaccordance with a conventional method.

[0005] Referring to FIG. 1A, an n-type well 13 is formed in asemiconductor substrate 11 formed therein a field oxidation layer 12 asa device isolation layer. A gate oxidation layer 14 and a gate electrode15 are formed on a selected region on the semiconductor substrate 11. Ap-type channel region 16 is formed below the gate oxidation layer 14 inthe semiconductor substrate 11. And, p-type source/drain regions 17 areformed with adjoining to the p-type channel region 16 in aligning bothedges of the gate electrode 14.

[0006] In the prior art shown in FIG. 1A, curing defects generated by anion implantation or an activation of dopants is realized by annealing ata high temperature at one time during a well annealing without anannealing process for an additional electrical activation with respectto the channel regions or by a thermal oxidation process of a gateoxidation layer.

[0007] And, after the forming of the p-type source/drain regions 17,crystal defects necessarily generated during an ion implantation areremoved and an annealing process is performed to activate the dopants.At this time, the annealing performed by raising a temperature at a lowrising temperature velocity to a maximum process temperature at a time.

[0008] But, as shown in FIG. 1B, although the crystalline defects can becured as the annealing process is proceeded at a high temperature duringa long time, as a channel size of device becomes to decrease, dopants ofthe p-type channel regions 16 move into a bottom portion of the n-typewell 13, inactivated dopants in the source/drain regions combine withvacancy to become an intrusion-type defect(x) and the intrusion-typedefect(x) is diffused to an end portion of the bottom portion of thegate electrode 15 and the semiconductor substrate 11 in the form ofbulk. Since borons as dopants of the p-type channel regions 16 aresegregated to the intrusion-type defect(x) and a concentrationnonuniformity of dopants is generated in the p-type channel regions 16,it is difficult to obtain a uniform distribution of dopants in a shallowchannel region.

[0009] Also, as the device becomes smaller the threshold voltage becomeslarger, in order to control this, although a doping concentration of thep-type channel region 16 becomes to increase, since a local annealingprocess for the p-type channel regions 16 does not implement in aconventional method, there is a problem that a local concentrationgradient, i.e., a variation width of the threshold voltage in responseto the nonuniformity of the dopants, becomes to increase.

[0010] Furthermore, after the formation of the p-type source/drainregions, conditions of annealing for the defect remove and an electricalactivation of the impurities has a very high thermal budget in a highdensity integrated device with a shallow junction and a small size and amaintaining time is nearly ranged from 10 seconds to 20 seconds at amaximum process temperature. Such conditions cause the mobility to bereduced at a surface as diffusions are occurred in a longitudinaldirection and a horizontal direction of junction, as a result, a drainsaturation current is decreased and a dose of dopants implanted by adopant diffusion is decreased to thereby reduce a contact resistance.

[0011] Therefore, the diffusion of dopants in the implanted channelregions is suppressed by lowering a thermal burden and the uniformity ofdopants in the channel regions by preventing the segregation to thefield oxidation layer, and also another thermal treatment process isrequired to recover the crystalline defect layer damaged during the ionimplantation to form the source/drain regions and to electricallyactivate the dopants.

SUMMARY OF THE INVENTION

[0012] It is, therefore, an object of the present invention to providesolve the above-described problems of the conventional method and toprovide a method for forming a p-channel metal-oxide semiconductor(PMOS)device suitable for reducing the width of change of a threshold voltageby preventing a deterioration of a uniformity of dopants due to outdiffusion and segregation of the dopants implanted into channel regions.

[0013] It is another object of the present invention to provide a methodfor forming a PMOS device having a shallow junction and a low contactresistance.

[0014] It is another object of the present invention to provide a methodfor forming a PMOS device suitable for minimizing diffusions of channeland source/drain regions and for suppressing a movement of intrudingtype defects injected by an inactivation of dopants.

[0015] In accordance with one aspect of the present invention, there isprovided a method for forming a p-channel metal-oxidesemiconductor(PMOS) device, the method includes the steps of: forming achannel region below a surface of a semiconductor substrate; activatingdopants implanted into the channel region through a first annealingprocess performed twice by rising temperature velocities different toeach other; forming a gate oxidation layer and a gate electrode on thesemiconductor substrate subsequently; forming a source/drain regions atboth sides of the gate electrode in the semiconductor substrate; andactivating dopants implanted into the source/drain regions through asecond annealing process performed at the same conditions of the firstannealing process.

[0016] In accordance with another aspect of the present invention, thereis provided a method for forming a PMOS device, wherein each of thefirst annealing and the second annealing processes are includes a firststep for first annealing by a velocity of a first rising temperature toa first process temperature at which a solid phase polycrystallinegrowth is occurred and a second step for annealing by a velocity of asecond rising temperature from the first process temperature to a secondprocess temperature of a maximum process temperature, respectively,wherein the velocity of the second rising temperature is relativelylarger than that of the first rising temperature.

[0017] In accordance with another aspect of the present invention, thereis provided a method for forming a PMOS device, wherein the firstprocess temperature is ranged from 500• to 650• during the firstannealing process and the velocity of the first rising temperature isranged from 20•/sec to 50•/sec.

[0018] In accordance with another aspect of the present invention, thereis provided a method for forming a PMOS device, wherein during thesecond annealing the second process temperature is ranged from 650• to900•-1050• and the velocity of the second rising temperature is rangedfrom 100•/sec to 200•/sec.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects and features of the instant inventionwill become apparent from the following description of preferredembodiments taken in conjunction with the accompanying drawings, inwhich:

[0020]FIG. 1A is a cross-sectional diagram showing a p-channelmetal-oxide semiconductor(PMOS) device in accordance with a conventionalmethod;

[0021]FIG. 1B shows a diagram representing a diffusion and segregationof boron in accordance with a conventional method;

[0022]FIG. 2 illustrates a flow chart of PMOS device in accordance witha preferred embodiment of the present invention; and

[0023]FIGS. 3A to 3D are cross-sectional views showing a method formanufacturing the PMOS device shown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, a preferred embodiment of the present invention willbe described in detail referring to the accompanying drawings.

[0025] In the following preferred embodiments, methods for improvingshort channel characteristics are proposed by preventing borons fromsegregating to a semiconductor substrate as channel and bulk regions andby realizing a uniformity of dopants in channel regions. This isachieved by suppressing a component such as an intrusion defect into thesemiconductor substrate as the channel and bulk regions by reducinginactivated amount with increasing an electrical activation of boronswhich are employed as dopant of source/drain regions in a device havinga short channel size, particularly in a p-channel metal-oxidesemiconductor (PMOS) device.

[0026]FIG. 2 illustrates a flow chart of PMOS device in accordance witha preferred embodiment of the present invention.

[0027] As shown in FIG. 2, a method for manufacturing a PMOS deviceincludes a process(S1) for forming an n-type well, a process(S2) forforming a p-type channel region, a process(S3) of first annealing, aprocess(S4) for forming a gate oxidation layer and a gate electrode, aprocess(S5) for forming p-type source/drain regions and a process(S6) ofsecond annealing.

[0028] Here, the first annealing process(S3) is performed to activatedopants implanted into channel regions, this process(S3) is performedbefore the formation of gate oxidation, and after a first annealing isperformed at a temperature range from 500▾ to 650▾ by a low temperaturerising speed of 20˜50▾/sec, a second annealing is performed at atemperature range from 650▾ to 900˜1050▾ by a high temperature risingspeed of 100˜200 ▾/sec. A temperature maintaining time is 0˜1 secondduring the second annealing, the temperature rising speed is ranged from100 to 200 ▾/sec, the first annealing is performed at a nitrideatmosphere to prevent borons implanted into the p-type channel regionsfrom slipping away from a surface and oxygen is supplied thereto withmaintaining an oxygen rate with respect to the nitride below 10%.

[0029] And, the second annealing process(S6) is performed to activatedopants implanted into the source/drain regions, after the process (S6)is performed at a temperature range from 500▾ to 650▾ by a lowtemperature rising speed of 20˜50 ▾/sec, a second annealing is performedat a temperature range from 650▾ to 900˜1050▾ by at a high temperaturerising speed of 100˜200▾/sec. At this time, the boron(B) implanted intothe p-type source/drain regions is prevented from out diffusing tooutside of a surface by supplying a small amount of oxygen during thefirst annealing.

[0030] As described above, by performing the annealing to activate thedopants implanted into the channel regions and the source/drain regionsat a very high temperature rising speed, the diffusion of dopants isreduced. And, since an exposing time and a maintaining time is short anda thermal burden is very low, the dopants implanted therein keep theirprofiles, as a result, a concentration becomes low and a mobility ofcarrier becomes to increase, a punch voltage is increased by keeping ahigh density of concentration by moving a small amount of dopants to thesurface and the bulk in Rp and a concentration of a junction part in thebulk becomes low to reduce a parasitic capacitance.

[0031]FIGS. 3A to 3D are cross-sectional views showing a method formanufacturing the PMOS device shown in FIG. 2.

[0032] As shown in FIG. 3A, after a field oxidation layer 22 as a deviceisolation layer is formed on a predetermined region of a semiconductorsubstrate 21 by a well known shallow trench isolation(STI) method or alocal oxidation of silicon(LOCOS) method, a screen oxide layer 23 isformed on the semiconductor substrate 21. At this time, the screen oxidelayer 23 is employed for preventing lattice damages from following ionimplantation processes and it may be formed of a thermal oxide bythermal oxidizing the surface of the semiconductor substrate 21.

[0033] In an ensuing step, after a mask 24 to expose an active region ona top surface of the semiconductor substrate 21 is formed, an n-typewell region 25 is formed by ion implanting an n-type dopant such asarsenic(As) into the active region of the semiconductor substrate 21exposed by the mask 24.

[0034] In a following step, with remaining the mask 24, an ion such as apure boron(_(IIB)) or a boron diflorin(BF₂) is implanted to form a boronimplanted p-type channel region 26. At this time, if the pureboron(_(IIB)) is implanted, a dose of 1 10¹²▾ 1 10¹³ ions/cm² isimplanted at a range of 10 keV▾ 40 keV and if the boron diflorin(BF₂) isimplanted, a dose of 1 10¹²▾ 1 10¹³ ions/cm² is implanted at a range of25 keV▾50 keV.

[0035] As shown in FIG. 3B, after the removal of the mask 24 and thescreen oxide layer 23, after an ion implantation for forming the p-typechannel region 26, the first annealing process having a small diffusionand a high electrical activation is performed in such a way that thep-type channel region 26 have a retrograde profile. Thus, after thefirst annealing the p-type channel region 26 becomes an electricallyactivated p-type channel region 26 a.

[0036] For example, after the first annealing is performed at atemperature range from 500▾ to 650▾ by a low temperature rising speed of20˜50▾/sec, a second annealing is performed at a temperature range from650▾ to 900˜1050▾ by at a high temperature rising speed of 100˜200▾/sec.

[0037] First, considering the first annealing, during the firstannealing it is performed at a temperature range from 500▾ to 650▾ by alow temperature rising speed of 20˜50▾/sec to generate a solid phasepolycrystal growth at a temperature range from 500▾ to 650▾, therebycrystallizing an amorphous layer generated by the ion implantationtoward the surface gradually.

[0038] And, to prevent the boron implanted into the electricallyactivated p-type channel region 26 a during the first annealing fromslip away to the outside of the surface it is performed at a nitrideatmosphere, and oxygen is supplied with maintaining an oxygen rate withrespect to the nitride below 10% so as to reduce the out diffusion ofborons(B) toward outside of the surface. That is, by supplying oxygen, anarrow oxide layer(not shown) is formed on the surface of thesemiconductor substrate 21, thereby increasing an amount of remainingborons(B) by preventing the borons(B) implanted into the electricallyactivated p-type channel region 26 a during the first annealing fromslipping away toward the outside of the surface.

[0039] In a next step, considering the second annealing, it is performedat a temperature range from 650▾ to 900˜1050▾ by at a high temperaturerising speed of 100˜200▾/sec, wherein a temperature maintaining time isranged from 0 to 1 second.

[0040] Thereafter, during the first annealing and the second annealing,to obtain a uniform distribution over an entire surface of a wafer, thewafer is rotated with inserting a nitrogen gas.

[0041] Such a rapid temperature rising speed allows a diffusion ofborons(B), especially a diffusion to a side direction, as well asincreases an electrical activation of the p-type channel region 26 byremaining borons(B) above the solid solubility as the same time. Inother word, the solubility of dopants can be represented by a functionof temperature, although the second annealing is performed at a hightemperature, a high solubility can be maintained due to a short exposuretime and a short maintaining time.

[0042] Similar to the second annealing, if the temperature rapidlyrising to a maximum process temperature, the mobility of borons(B) issuppressed in the p-type channel region 26 a as well as the degree ofinactivation is reduced by increasing the electrical activation of theborons(B).

[0043] Since the first annealing as described above is a hightemperature rising annealing, the first annealing has a sufficient lowthermal burden, as a result diffusions especially to the side directionand the field oxidation layer 22 are reduced and a profile of supersteep retrograde(SSR) channel is realized to thereby improve a shortchannel effect, wherein the profile represents that the SSR channelbecomes a low concentration around the surface thereof, becomes amaximum concentration at a projection of range(Rp) and becomes a lowconcentration at the bulk.

[0044] As shown in FIG. 3C, after a gate oxide layer 27, a gateelectrode 28 are subsequently formed on a semiconductor substrate 21formed thereon the p-type channel region 26 a, p-type source/drainregions 29 is formed by ion implanting an ion such as a pureboron(_(IIB)) or a boron diflorin(BF₂) by utilizing the gate electrode28 as a mask. At this time, conventionally an ion implantation to formthe p-type source/drain regions 29 is performed by using a pureboron(_(IIB)) or a boron diflorin(BF₂). If the pure boron (_(IIB)) isemployed, a dose of 1 10¹⁵▾ 4 10¹⁵ ions/cm² is implanted at a range of10 keV▾ 20 keV and if the boron diflorin(BF₂) is utilized, a dose of 110¹⁵▾ 4 10¹⁵ ions/cm² is implanted at a range of 200 eV▾ 5 keV.

[0045] As shown in FIG. 3D, after the p-type source/drain regions 29 isformed, in order to recover an electrical activation and the damagedsilicon lattice defects of the borons, the second annealing isperformed. At this time, the second annealing is different from theconventional method, which raises the temperature to a maximum processtemperature by a low temperature rising speed, in that raises theprocess temperature by twice, therefore, after the second annealing, thep-type source/drain regions 29 becomes an electrically activated p-typesource/drain regions 29 a.

[0046] Here, after the second annealing is performed at a temperaturerange from 500▾ to 650▾ by at a low temperature rising speed of20˜50▾/sec, it is performed at a temperature range from 650▾ to900˜1050▾ by at a high temperature rising speed of 100˜200▾/sec.

[0047] First, considering the first annealing, during the firstannealing it is performed at a temperature range from 500▾ to 650▾ by alow temperature rising speed of 20˜50▾/sec to generate a solid-phasepolycrystal growth at a temperature range from 500▾ to 650▾, therebycrystallizing an amorphous layer generated by the ion implantationtoward the surface gradually.

[0048] And, to prevent the boron implanted into the electricallyactivated p-type source/drain regions 29 a during the first annealingfrom slip away to the outside of the surface it is performed at anitride atmosphere, and oxygen is supplied with maintaining an oxygenrate with respect to the nitride below 10% so as to reduce the outdiffusion of borons(B) toward outside of the surface. That is, bysupplying oxygen, a narrow oxide layer(not shown) is formed on thesurface of the semiconductor substrate 21, thereby increasing an amountof remaining borons(B) by preventing the borons(B) implanted into theelectrically activated p-type source/drain regions 29 a during the firstannealing from slipping away toward the outside of the surface.

[0049] In a next step, considering the second annealing, it is performedat a temperature range from 650▾ to 900˜1050▾ by at a high temperaturerising speed of 100˜200▾/sec, wherein a temperature maintaining time isranged from 0 to 1 second.

[0050] Such a rapid temperature rising speed allows a diffusion ofborons(B), especially a diffusion to a side direction, as well asincreases an electrical activation of the p-type source/drain regions 29a by remaining borons(B) above the solid solubility as the same time. Inother word, the solubility of dopants can be represented by a functionof temperature, although the second annealing is performed at a hightemperature, a high solubility can be maintained due to a short exposuretime and a short maintaining time.

[0051] Similar to the second annealing, if the temperature rapidlyrising to a maximum process temperature, the mobility of borons(B) issuppressed in the p-type source/drain regions 29 a as well as the degreeof inactivation is reduced by increasing the electrical activation ofthe borons(B).

[0052] That is, by reducing the degree of inactivation of the borons(B), the degree of combination between the borons and vacancy isreduced, and the segregation of borons(B) in the p-type channel regionby decreasing an amount of intrusion-type defects in the source/drainregions 29 a implanted into a direction of a bottom portion of the gateelectrode 28 of the p-type channel region 26 a.

[0053] Therefore, the uniformity of borons(B) in the p-type channelregion 26 a is improved by the second annealing, thereby improving ashort channel characteristics, i.e., a threshold voltage difference anda drop in accordance/with a channel position, a leakage current at anatmosphere and a drop of punch voltage between the source region and thedrain region.

[0054] On the other hand, borons may be slipped away toward outside ofthe surface during the second annealing, but since a shallow oxidelayer(not shown) is formed on a top surface of the semiconductorsubstrate 21 by supplying oxygen during the first annealing, the boronsare prevented from slipping away.

[0055] And, during the first annealing and the second annealing, toobtain a uniform distribution over an entire surface of a wafer, thewafer is rotated with inserting a nitrogen gas.

[0056] The present invention described above can be applicable to amemory device and an application specific integrated circuit(ASIC)device and it can propose an annealing technique for providing anapplication technology suitable for a high density integration circuitwith decreasing its channel and junction in size.

[0057] And also, the present invention described above can keep aprofile of a shallow channel in a channel region and can reduce avariation width of a threshold voltage by controlling a nonuniformity oflocal dopants by suppressing a segregation of dopants toward a sidedirection and a field oxidation layer.

[0058] In addition, the present invention can form a junction required ashallow junction and a low resistance by suppressing diffusions ofdopants implanted into source/drain regions by increasing a solubilityof dopants through two times of annealing processes.

[0059] While the present invention has been described with respect tothe particular embodiments, it will be apparent to those skilled in theart that various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A method for forming a p-channel metal-oxidesemiconductor(PMOS) device, the method comprises the steps of: forming achannel region below a surface of a semiconductor substrate; activatingdopants implanted into the channel region through a first annealingprocess performed twice by rising temperature velocities different toeach other; forming a gate oxidation layer and a gate electrode on thesemiconductor substrate subsequently; forming a source/drain regions atboth sides of the gate electrode in the semiconductor substrate; andactivating dopants implanted into the source/drain regions through asecond annealing process performed at the same conditions of the firstannealing process.
 2. The method of claim 1, wherein each of the firstannealing and the second annealing processes are includes a first stepfor first annealing by a velocity of a first rising temperature to afirst process temperature at which a solid phase polycrystalline growthis occurred and a second step for annealing by a velocity of a secondrising temperature from the first process temperature to a secondprocess temperature of a maximum process temperature, respectively,wherein the velocity of the second rising temperature is relativelylarger than that of the first rising temperature.
 3. The method of claim2, wherein the first process temperature is ranged from 500• to 650•during the first annealing process and the velocity of the first risingtemperature is ranged from 20•/sec to 50•/sec.
 4. The method of claim 2,wherein during the second annealing the second process temperature isranged from 650• to 900•˜1050• and the velocity of the second risingtemperature is ranged from 100•/sec to 200•/sec.
 5. The method of claim2, wherein the first annealing process is performed at a nitrideatmosphere and oxygen is supplied with maintaining an oxygen rate withrespect to the nitride below 10%.
 6. The method of claim 2, wherein atemperature maintaining time is ranged from 0 second to 1 second duringthe second annealing process.
 7. The method of claim 2, wherein thefirst annealing process and the second annealing process are performedby rotating a wafer, respectively.
 8. The method of claim 1, wherein thefirst annealing process and the second annealing process are performedby rotating a wafer, respectively.
 9. The method of claim 1, wherein thestep of forming the channel region implants pure boron in dose of1×1012˜1×1013 ions/cm2 in an energy of 10 keV˜40 keV or implants borondiflorin in dose of 1×1012˜1×1013 ions/cm2 in an energy of 25 keV˜50keV.
 10. The method of claim 1, wherein the step of forming thesource/drain regions implants pure boron or boron diflorin in dose of1×10¹⁵˜4×10¹⁵ ions/cm2, the pure boron is implanted in an-energy of 10keV˜20 keV and the boron di diflorin is implanted in an energy of 200eV˜5 keV.